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Description: SDRAM控制器的VHDL代码在FGPA中的综合与实现-SDRAM controller VHDL code FGPA and implementation of integrated
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Size: 2383872 |
Author: Mr Yang |
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Description: DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
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Size: 432128 |
Author: robert.wang |
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Description: It s a SDRAM Controller reference design. It had been tested in many projects.
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Size: 466944 |
Author: greyzhuang |
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Description: SDRAM控制器HDL实现,sdram为美光公司的-sdram controller
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Size: 3072 |
Author: paladin |
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Description: SDRAM存储器芯片,FPGA的接口控制,VHDL语言编写-SDRAM memory chips, FPGA interface control, VHDL language
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Size: 776192 |
Author: wang |
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Description: 关于DDR2 SDRAM 控制器的相关论文资料-ddr2_sdram_controller
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Size: 5675008 |
Author: 王颖伟 |
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Description: Simple SDRAM Controller.
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Size: 3072 |
Author: vasil |
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Description: DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code
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Size: 13312 |
Author: tom |
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Description: Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现-Hynix' s 8M Byte SDR SDRAM Simulation of the Verilog language
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Size: 54272 |
Author: tom |
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Description: sdram的设计文档和参考源码。嵌入式开发中很难找到的源码。-sdram design documents and source code
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Size: 159744 |
Author: wisebear |
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Description: SDRAM VHDL/Verilog simulation model
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Size: 7168 |
Author: Ravi |
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Description: 一个项目工程,硬件包含XINLINX FPGA,配置FLASH,串口,SDRAM,与以太网芯片DM9000A,实现数据采集,以太网传输,电路验证完全正确,请放心使用,SPARTAN 3E 的BGA引脚320个,不容易布板,可以参考使用的。要FPGA实现网络通信也可以参考电路,B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, configuration FLASH, serial port, SDRAM, and Ethernet chips DM9000A, data acquisition, Ethernet transmission, circuit verification is completely correct, please rest assured that the use of, SPARTAN 3E' s 320-pin BGA it is not easy layout, you can reference to use. To achieve network communication FPGA also can refer to the circuit, because the product upgrades so publicly.
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Size: 915456 |
Author: rong |
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Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory.
This code is Verilog.
This code is based Xilinx FPGA Playform.
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Size: 488448 |
Author: peace |
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Description: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM (JEDEC DDR400
(PC3200) 标准)控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400
(PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
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Size: 408576 |
Author: 陈阳 |
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Description: 4 multi port sdram controller
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Size: 357376 |
Author: waters |
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Description: 内附doc是DDR SDRAM 参考设计文档;model包含SDRAM VHDL的模型;simulation包含VHDL测试平台、modelsim工程文、设计
库函数;source包含vhdl源文件;synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test bench, modelsim project text, design library function source contains the vhdl source file synthesis comprehensive document that contains the project.
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Size: 886784 |
Author: 陈少华 |
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Description: SDRAM 驱动,Verilog HDL源码-SDRAM-driven, Verilog HDL source code
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Size: 297984 |
Author: 刘越 |
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Description: xilinx公司SDRAM的参考设计,调试成功-xilinx' s SDRAM reference design, debug successful
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Size: 128000 |
Author: 陈俊 |
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Description: SDRAM module Verilog HDL-SDRAM module Verilog HDL
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Size: 6144 |
Author: Jack |
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Description: DDR SDRAM技术总结 介绍DDR SDRAM的一些概念和难点 着重讲解主流DDRII的技术 最后结合硬件设计提出一些参考 -DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware design combined with some reference
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Size: 2262016 |
Author: 董萌 |
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